1. Field of Invention
The present invention relates generally to an improved ultra large-scale integrated (ULSI) circuit having a copper sulfide interface layer. More particularly, the present invention relates to the fabrication of ULSI using a dual damascene process in conjunction with using a copper sulfide interface layer.
2. Description of Prior Art
The dual damascene process, in which metal is buried inside patterned grooves in a substrate, is frequently used and has become one of the best methods for fabricating USLI circuits. Conventionally, metallic interconnects are formed by depositing a metallic layer over an insulating layer, for example, a silicon dioxide layer. Then, the insulating layer is etched to form a pattern of predefined conductive lines so that a vertical via hole can be formed between conductive layers. Thereafter, metallic material is deposited into the via hole to complete vertical connection between the conductive layers forming an interconnect. Conventionally, there can be a passivation layer formed between the two conductive layers. (See FIG. 1,14)
Workers in the art are aware that when the passivation layer or any other layer that is positioned on the top of a lower interconnect 12 is etched away from the bottom of the via hole the sputtering of the copper onto the via hole side walls 28 usually occurs. Consequently, copper ions have migrated into the dielectric material, which would result in a change in device properties, and ultimately not being able to use the device. The current invention makes the use of a barrier layer optional thus saving a costly step in production of the devices. Others have striven to solve this problem by lining the via hole with barrier metal layers (See FIG. 2, 24). For Example, U.S. Pat. No. 5,933,758 (Jain) teaches a barrier layer over a dual damascene opening. U.S. Pat. No. 5,693,563 (Teong) shows dual barrier layers in a dual damascene process. U.S. Pat. No. 5,451,542 (Ashby) teaches an S surface passivation process. Even when the barrier layer is used there is still a second problem and that is that these barrier layers usually have thin holes throughout, so that when the copper is deposited in the via hole to form an upper interconnect. The copper diffuses into the dielectric materials, which again would result in a change in device properties, and ultimately not being able to use the device.
Other prior art have shown the use of copper sulfide as a layer. For example, U.S. Pat. Nos. 5,953,628 and 5,863,834 (Kawaguchi and Kawaguchi et al. respectively) teach the use of a copper sulfide on copper wiring. However, the use of copper sulfide is for preventing the oxidation of copper wiring, and it completely surrounds the copper wiring.